Ventana Micro Systems has a total of 31 patents globally, out of which 6 have been granted. Of these 31 patents, more than 96% patents are active. The United States of America is where Ventana Micro Systems has filed the maximum number of patents. Parallelly, The United States of America seems to be the main focused R&D center and also USA is the origin country of Ventana Micro Systems. Ventana Micro Systems was founded in 2018. The Company provides technology solutions. The Company offers data center class high-performance RISC-V CPUs with extensible instruction set capability delivered in the form of multi-core chiplets. Do read about some of the most popular patents of Ventana Micro Systems which have been covered by us in this article and also you can find Ventana Micro Systems patents information, the worldwide patent filing activity and its patent filing trend over the years, and many other stats over Ventana Micro Systems patent portfolio.
How many patents does the Founder and CEO of Ventana Micro Systems have?The Founder and CEO Balaji Baktha has 1 patent.
How many patents does Ventana Micro Systems have?Ventana Micro Systems has a total of 31 patents globally. These patents belong to 8 unique patent families. Out of 31 patents, 30 patents are active.
How Many Patents did Ventana Micro Systems File Every Year?Are you wondering why there is a drop in patent filing for the last two years? It is because a patent application can take up to 18 months to get published. Certainly, it doesn’t suggest a decrease in the patent filing.
|Year of Patents Filing or Grant||Ventana Micro Systems Applications Filed||Ventana Micro Systems Patents Granted|
How many Ventana Micro Systems patents are Alive/Dead?Worldwide Patents
How Many Patents did Ventana Micro Systems File in Different Countries?All the Patents were filed by Ventana Micro Systems in the United States of America.
Where are Research Centers of Ventana Micro Systems Patents Located?The Research Centre for all the Ventana Micro Systems patents is the United States of America.
10 Best Ventana Micro Systems PatentsUS20220067155A1 is the most popular patent in the Ventana Micro Systems portfolio. It has received 3 citations so far from companies like IBM.
Below is the list of 10 most cited patents of Ventana Micro Systems:
|Publication Number||Citation Count|
What Percentage of Ventana Micro Systems US Patent Applications were Granted?Ventana Micro Systems (Excluding its subsidiaries) has filed 29 patent applications at USPTO so far (Excluding Design and PCT applications). Out of these 4 have been granted leading to a grant rate of 100.0%. Below are the key stats of Ventana Micro Systems patent prosecution at the USPTO.
Which Law Firms Filed Most US Patents for Ventana Micro Systems?
|Law Firm||Total Applications||Success Rate|
|Huffman Law Group||29||100.00%|
List of Ventana Micro Systems Patents
|Ventana Micro Systems Patents||Title|
|US11687466B1||Translation Lookaside Buffer Consistency Directory For Use With Virtually-Indexed Virtually-Tagged First Level Data Cache That Holds Page Table Permissions|
|US11625479B2||Virtually-Tagged Data Cache Memory That Uses Translation Context To Make Entries Allocated During Execution Under One Translation Context Inaccessible During Execution Under Another Translation Context|
|US11620377B2||Physically-Tagged Data Cache Memory That Uses Translation Context To Reduce Likelihood That Entries Allocated During Execution Under One Translation Context Are Accessible During Execution Under Another Translation Context|
|US11416406B1||Store-To-Load Forwarding Using Physical Address Proxies Stored In Store Queue Entries|
|US11416400B1||Hardware Cache Coherency Using Physical Address Proxies|
|US11397686B1||Store-To-Load Forwarding Using Physical Address Proxies To Identify Candidate Set Of Store Queue Entries|
|US20230244778A1||Physically-Tagged Data Cache Memory That Uses Translation Context To Reduce Likelihood That Entries Allocated During Execution Under One Translation Context Are Accessible During Execution Under Another Translation Context|
|US20220358047A1||Microprocessor That Prevents Same Address Load-Load Ordering Violations|
|US20220358210A1||Conditioning Store-To-Load Forwarding (Stlf) On Past Observations Of Stlf Propriety|
|US20220358046A1||Using Physical Address Proxies To Handle Synonyms When Writing Store Data To A Virtually-Indexed Cache|
|US20220358045A1||Physical Address Proxies To Accomplish Penalty-Less Processing Of Load/Store Instructions Whose Data Straddles Cache Line Address Boundaries|
|US20220358048A1||Virtually-Indexed Cache Coherency Using Physical Address Proxies|
|US20220357955A1||Store-To-Load Forwarding Correctness Checks At Store Instruction Commit|
|US20220358052A1||Generational Physical Address Proxies|
|US20220358039A1||Physical Address Proxy (Pap) Residency Determination For Reduction Of Pap Reuse|
|US20220358040A1||Unforwardable Load Instruction Re-Execution Eligibility Based On Cache Update By Identified Store Instruction|
|US20220358037A1||Physical Address Proxy Reuse Management|
|US20220358043A1||Write Combining Using Physical Address Proxies Stored In A Write Combine Buffer|
|US20220358038A1||Microprocessor That Prevents Same Address Load-Load Ordering Violations Using Physical Address Proxies|
|US20220358044A1||Store-To-Load Forwarding Correctness Checks Using Physical Address Proxies Stored In Load Queue Entries|
|US20220108013A1||Processor That Mitigates Side Channel Attacks By Refraining From Allocating An Entry In A Data Tlb For A Missing Load Address When The Load Address Misses Both In A Data Cache Memory And In The Data Tlb And The Load Address Specifies A Location Without A Valid Address Translation Or Without Permission To Read From The Location|
|US20220107784A1||Processor That Mitigates Side Channel Attacks By Providing Random Load Data As A Result Of Execution Of A Load Operation That Does Not Have Permission To Access A Load Address|
|US20220108012A1||Processor That Mitigates Side Channel Attacks By Prevents Cache Line Data Implicated By A Missing Load Address From Being Filled Into A Data Cache Memory When The Load Address Specifies A Location With No Valid Address Translation Or No Permission To Read From The Location|
|US20220067156A1||Processor That Mitigates Side Channel Attacks By Preventing Cache Memory State From Being Affected By A Missing Load Operation By Inhibiting Or Canceling A Fill Request Of The Load Operation If An Older Load Generates A Need For An Architectural Exception|
|US20220067155A1||Processor That Mitigates Side Channel Attacks By Preventing All Dependent Instructions From Consuming Architectural Register Result Produced By Instruction That Causes A Need For An Architectural Exception|
|US20220067154A1||Processor That Mitigates Side Channel Attacks By Expeditiously Initiating Flushing Of Instructions Dependent Upon A Load Instruction That Causes A Need For An Architectural Exception|
|US20220027468A1||Microprocessor That Conditions Store-To-Load Forwarding On Circumstances Associated With A Translation Context Update|
|US20220027467A1||Processor That Prevents Speculative Execution Across Translation Context Change Boundaries To Mitigate Side Channel Attacks|
|US20220027460A1||Microprocessor Core With A Store Dependence Predictor Accessed Using A Translation Context|
|US20220027459A1||Microprocessor That Prevents Store-To-Load Forwarding Between Different Translation Contexts|
|US20220358209A1||Thwarting Store-To-Load Forwarding Side Channel Attacks By Pre-Forwarding Matching Of Physical Address Proxies And/Or Permission Checking|